As is well known, microprocessors or central processing units (“CPUs”) for personal computers, workstations, and servers now require very sophisticated mechanisms for the controlling the supply voltage reference to which they are connected. These references should meet high precision requirements both under rest conditions and under load transient conditions.
Suitable current or voltage controller devices are thus used that are able to supply suitable voltage references. The requirements of this specific field have led to the use of, for these controller devices or “regulators”, multiphase buck topologies that are the most suitable for meeting the multiple requirements for these references.
Such a regulator comprises, for example, a converter of the DC-DC interleaving type that is realized by connecting in parallel N DC-DC converters in Buck configuration, also known as step-down configuration (i.e., connecting together their input and output terminals driven in and out of phase, or in an interleaved way).
The converters are interleaved with each other for a value equal to 1/N so as to ensure a low oscillation or ripple of the output voltage value and a low value for the efficient current value or input RMS (“Root-Mean-Square”).
A multiphase regulator essentially comprises a controller connected to n buffers or phases (multiphase configuration), which in turn essentially comprise pairs of switches, known as High Side and Low Side, driven by the controller so as to supply the power requested by a CPU that is connected to the output terminal of the multiphase regulator.
To meet very fast and significant load transients (e.g., up to 100 A in 50 ns), the multiphase regulators require non-linear controls that are activated in the presence of load transients and simultaneously turn on all of the available phases for sustaining the value of the voltage on its output terminal.
Moreover, multiphase regulators comprise control mechanisms for avoiding an unbalance of the currents between the phases, so as to ensure the thermal balance and avoid excessive stress on the components of its power stages (and in particular, of the power MOS transistors and the inductors).
The operation of a multiphase regulator is well known. FIG. 1 shows a block diagram of a multiphase regulator of the buck type with N phases.
The multiphase regulator 1 has a controller 6 connected to n buffers or phases Fi, which each include a pair of switches, High Side and Low Side, driven through respective driving circuits Dri by the controller 6, so as to supply a requested power (for example by a CPU) to the output terminal OUT of the multiphase regulator 1.
In more detail, each phase Fi of the multiphase regulator 1 comprises a High Side switch SWHSi connected in series to a Low Side switch SWLSi between first and second voltage references, in particular an input voltage Vin and ground GND.
Each phase Fi also comprises an inductor Li coupled between ground GND and a switch node, or phase node, that is intermediate between the switches SWHSi and SWLSi. The multiphase regulator 1 also comprises an output capacitor Cout coupled between the output terminal OUT and ground GND. Across the capacitor Cout there is an output voltage value Vout.
The controller 6 supplies a modulation signal PWMi of the PWM type to the High Side switches SWHSi and Low Side switches SWLSi of the phases Fi, which are sensitive to the level of the signal PWMi. In particular, the High Side switches are on and the Low Side switches are off if PWMi=1, and vice versa the High Side switches are off and the Low Side switches are on if PWMi=0. For this purpose, the controller 6 comprises a PWM signal generator 2 and an oscillator 3 of the interleaving type.
In particular, the oscillator 3 is connected to the generator 2 and supplies it with a ramp signal RAMPi for each phase Fi, and the generator 2 supplies respective modulation signals PWMi to the driving blocks Dri of the phases Fi.
In the exemplary multiphase regulator described in Italian Patent Application No. MI2008A 001066 (which is also assigned to the Assignee of the present invention), the oscillator 3 applies a modulation in frequency and a modulation index to minimize the entity of the harmonic at the switching frequency FSW of the multiphase regulator 1.
The multiphase regulator 1 also comprises a current sharing control circuit 4 that receives the current value ILi of each phase Fi and supplies a balance voltage value VBALANCE—i for each phase Fi, with such balance voltage VBALANCE—i being added by an adder node Xi with a signal COMP supplied at the output terminal O of an error amplifier 5 of the multiphase regulator 1.
The current sharing control circuit 4 substantially provides information on the unbalance of the currents in the phases Fi of the multiphase regulator 1. In particular, the current sharing control circuit 4 measures the current flowing in each single inductor Li of the phases Fi and compares this with an average current IAVG. A shift of the current of a phase from this average current thus results in a smaller or greater duty cycle of the balance voltage VBALANCE—i generated for that phase.
The error amplifier 5 has a first input terminal I1 that receives a reference voltage value REF and a second input terminal I2 connected, through a first impedance ZFB, to the output terminal OUT of the multiphase regulator 1, and also connected, through a second impedance ZF, to its output terminal O, which in turn is connected to the adder nodes Xi.
In the case of a load transient, according to the use of linear or non-linear techniques, the multiphase regulator 1 responds by turning on or not all of the N available phases. A description of these techniques can be found in European Patent Application No. EP 1 826 893 (Aug. 29, 2007), in the name of STMicroelectronics S.r.l.
FIGS. 2A and 2B show the response of a multiphase regulator having three phases in accordance with the principles of this European Patent Application. As shown in FIG. 2A, with a load applied, such a multiphase regulator, during a load transient, simultaneously turns on all of the three available phases.
As seen in the figure, the last phase turned on before the transient with load application is the phase F1, but due to the presence of an interleaving which flows temporally and independently from the load transient, the phase turned on immediately after the transient is again the phase F1 which, at this point, is also the one that carries more current.
Moreover, the loop, that is the current balance circuit 4 (current sharing loop), noting the unbalance of the currents, tries to correct the balance voltages to correct this current unbalance. The balance voltages, in correspondence with the adder nodes, are added to the signal COMP, which represents information on the output voltage, and their sums generate signals which identify respective control voltages which are compared with the corresponding ramp signals RAMPi for generating in turn respective modulation signals PWMi.
The result of this correction is a modulation signal PWM1 that is shorter than its due on the phase F1, and modulation signals PWM2 and PWM3 that are wider on the phases F2 and F3. This behavior generates a perturbation on the main control loop of the output voltage (i.e., the loop comprising the error amplifier 5) causing a lack of the orthogonality (i.e., the independence property) between the two control loops of the multiphase regulator 1, that is the main output voltage loop and the current balance (or current sharing) loop.
For regulating the output voltage VOUT, the main voltage loop should impose the duration of the turn-on Ton of the phases F1, F2, and F3 independently from the unbalance of the currents. To do this it is necessary for the bands of the two main voltage and current sharing loops to be very different from each other, in particular to be different by at least one decade.
The requirement of a very low band of the current sharing loop, however, jeopardizes the balance of the currents when the load frequency varies (i.e., when there are beats between the load frequency and the switching frequency of the regulator as a whole). This problem is described in greater detail in Italian Patent Application No. MI2008A 001066 (filed Jun. 13, 2008) in the name of STMicroelectronics S.r.l.
The same mechanism triggers in the case of a load transient under current release (load release), as shown in FIG. 2B. In particular, as shown in this figure, the last phase being turned on before the load release is the phase F3, subsequently the first ramp which is intercepted is not the one relative to the modulation signal of the phase F1, PWM1, (which is, theatrically, the one that should carry less current), but the one of the modulation signal of the phase F2, PWM2.
This behavior in the load release step generates the worst problems in the case of repeated load transients. The multiphase regulator 1 generates a frequency beat on the control voltage of the PWM modulation signals equal to the difference between the frequency of repetition of the load transients FL and the proper switching frequency FSW of the multiphase regulator itself.
In this situation, the current sharing loop cannot ensure the correct current balance due to the strong frequency beats and the low passing band of the same loop.
The result is a strong oscillation of the currents, as shown in FIG. 3A in the case of FSW=300 kHz and FL=305 kHz, which can lead to excessive stresses on the power components or even to a static unbalance of the currents, as shown in FIG. 3B in the case of FSW=300 kHz and FL=300 kHz, with disastrous consequences (for example, from the thermal design viewpoint of the motherboard containing the CPU that is controlled by this type of multiphase regulator.
Some technical solutions are known for overcoming these drawbacks and the problem of the beat of the currents during repeated load transients.
A solution known as Adaptive Firing Order (“AFO”) is described in U.S. Patent Application Publication No. 2008/0197824 (Aug. 21, 2008).
In this solution, the turn-on sequence of the phases is determined by a direct comparison of the currents of the phases. Two lists are used: a “standby list” and a “waiting list”. The phases in the “standby list” cannot be turned on while the phase which carries less current among those on the “waiting list” is instead turned on. Once turned on, this phase goes into the “standby list” while the phase that, in the “standby list”, carries less current is promoted from the “standby list” to the “waiting list”, and so on.
Although meeting the aim, this solution is not exempt from drawbacks. For example, the turn-on method used in the AFO solution does not allow the consecutive turn-on of the same phase; to turn it on again, there is at least a one clock cycle wait.
Moreover, the comparison is made directly on the read currents. However, it is well known that, in certain applications, the currents can be very noisy and very close to each other in relation to the switching frequency of the system as a whole and to the type of inductors as used.
The distinction of the current is also affected by a dynamics problem, in particular linked to the fact that, at low load, the current information is very small and thus more likely subject to offset and to switching noise of the multiphase regulator. This dependency on the application makes this method weak since the multiphase regulator could not distinguish at the best the lowest current and erroneously turn on one phase rather than another phase.
Moreover, the decision of the phase turn-on is exclusively made by the control between the currents to determine the lowest current.